Integrated circuits typically use one or more clock signals to synchronize components in the integrated circuit. Clock trees are used to branch these clock signals through buffers from a common source to components located in various areas on the integrated circuit. For example, a given source clock signal may feed into three buffers to produce three clock signals at a second branch level, which may feed into three more buffers to produce nine clock signals at a third branch level. Clock signals at any level can be used for clocking synchronous components to coordinate the functions within the integrated circuit. Therefore, the clock signals at any particular level have a predefined phase relationship to one another.
For various reasons, however, any two clock signals at the same level of the same clock tree may be slightly out of phase with one another or do not otherwise have the desired phase relationship. This phase difference between clock signals is called “clock skew.” Clock skew can have several causes. For example, the load experienced by one clock signal may introduce a delay into the clock tree branch that is different from the delay along another clock tree branch. Also, routing differences between clock tree branches can result in different resistance between the branches and therefore different propagation delays along the branches. Furthermore, changes in temperature, different applied voltages and tolerances in semiconductor fabrication processes can affect clock skew.